As ultra large-scale integrated circuits have continued to evolve, they have become more complex with the need to switch more and more output driver circuits at higher and higher speeds. In addition, an increase in the use of parallel processing has necessitated designing circuits with a high number of driver circuits to switch simultaneously at fast transition speeds and high currents. Since the effective inductance of semiconductor chips for these active switching circuits is directly related to the amount of power distribution noise, the driver circuit power connections are particularly sensitive to the noise created by the effective inductance inherent in simultaneous switching activity. Numerous techniques have been developed using decoupling capacitors to reduce power supply transients, ground bounce, and high frequency inductive delay.
The earliest techniques involved positioning the decoupling capacitors as discrete components on the printed circuit board adjacent to the integrated circuit device. However, the length of the connections of the decoupling capacitors to the integrated circuit devices added unwanted inductances and introduced further noise.
Since it is desirable to have the decoupling capacitors as close to the integrated circuit as possible to maximize the benefits of the decoupling capacitor, subsequent designs located the decoupling capacitors as small, discrete devices above or below the associated integrated circuit device. While this approach provided some improvement, the difficulty of making the manufacturing interconnections to the integrated circuit device or to the circuit board and the still relatively long connections continued to be less than optimal.
Subsequently, many different approaches were developed to photolithographically place the decoupling capacitors "on-chip" on the semiconductor chips themselves.
Where the decoupling capacitors were placed on the surface of the silicon chip as part of the integrated circuit, maximum reduction of negative effects was achieved, but at an exorbitant cost in highly valuable silicon real estate.
Where the decoupling capacitors were integrated over the circuitry of the semiconductor chips as part of the semiconductor manufacturing process, additional processing steps were required which introduced additional complexity, which reduced yield and made the resulting integrated circuits more expensive.
A simple, elegant solution has long been sought for providing inexpensive integrated circuit devices with decoupling capacitors that reduce power supply transients, ground bounce, and high frequency inductive delay. As indicated by the many different approaches to the inherent problems, a solution has long eluded those skilled in this art.